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From the Desk of the Vice Chancellor

Greetings!

As the Vice Chancellor of this premier university, I am extremely pleased to share this space to converse with all of you. The University of Madras is a post- sesquicentennial institution which has forged a glorious path for itself and has been the site for significant scientific discoveries as well as the beacon for national and regional societal transformation. It has successfully managed to hold aloft its tradition even while keeping up with the emerging trends. One reason for this is the way in which the university has kept alive its interactions with all the stakeholders.

The COVID 19 pandemic has introduced a ‘new normal’ and its impact is felt in the workings of the university as well. The students have been attending the lectures online. While online learning has the advantage of being anytime and anywhere, it has taken away the peer group interaction and peer learning which are integral aspects of the university experience. We look forward to welcoming you to the campus very soon. Meanwhile, our faculty and administration will continue to bring the best to the virtual classrooms. As students, you need to view the restrictions posed by the pandemic as a temporary deterrent. Your focus should be to gain the competencies to conduct application oriented research in order to evolve as useful citizens of our society.

Our university boasts of faculty with a high degree of knowledge and commitment to offer the best in teaching and research. Given the context of the pandemic, we need to redefine our teaching-learning processes to offer the best pedagogic experience to our students. Similarly, the post-pandemic era demands that we hone the employment potential and entrepreneurial capacity of our learners. This necessitates that we focus on sponsored research in cutting edge areas.

Our administrative staff have been the backbone of the university. While we move towards a transparent and complete e-governance model, we need more support from you. When the teaching-learning process at our university – from admission to certification -- is moving into the digital era, your skills and competencies need to keep pace.

At our university, we are gearing up for the final round of NAAC re-accreditation. This has offered us an opportunity to assess our Strengths, Weaknesses, Opportunities and Challenges. Further, it has made us more determined to reiterate our quality benchmarks in teaching, research and extension activities. We are aware of this responsibility and fully prepared for it because, our university has always encouraged individual thinking within the established frameworks. This is echoed in the words of Tim Burners Lee, who initiated the World Wide Web: “We are forming cells within a global brain and we are excited that we might start to think collectively. What becomes of us still hangs crucially on how we think individually.” Let us unite to make the educational experience at the University of Madras a synergy of the best minds and best thoughts.

Prof.Dr.S.Gowri

Vice-Chancellor
University of Madras

Dr. S. BalakumarM. Sc., M. Phil., Ph.D., FRSC (UK), FInstP (IOP, UK), SMIEEE (USA)

Professor
National Centre for Nanosciences and Nanotechnology
17

Awards

306

Publications

40

Seminars / Conference

31

Projects

14

Ph.D Awarded

8

Ph.D Present

Patents
S.No Title Description Patent Year Authority
1 CMP uniformity A new apparatus is provided that allows for uniform polishing of semiconductor surfaces. The single polishing pad of conventional CMP methods is divided into a split pad, the split pad allows for separate adjustments of CMP control parameters across the surface of the wafer. These adjustments can extend from the center of the wafer to its perimeter (along the radius of the wafer) thereby allowing for the elimination of conventional problems of non-uniformity of polishing between the center of the surface that is polished and the perimeter of the surface that is polished. 2001 U. S.Patent
2 Method to form shallow trench isolations A new method of fabricating shallow trench isolations has been achieved. A pad oxide layer is formed overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A protective layer is deposited overlying the silicon nitride layer. The protective layer, the silicon nitride layer, and the pad oxide layer are patterned to expose the semiconductor substrate where shallow trench isolations are planned. The semiconductor substrate is etched to form trenches for the planned shallow trench isolations. A large trench etching angle is used. The presence of the protective layer prevents loss of the silicon nitride layer during the etching. A trench filling layer is deposited overlying the protective layer and filling the trenches. The trench filling layer and the protective layer are polished down to complete the shallow trench isolations in the manufacture of the integrated circuit device. 2003 U. S.Patent
3 Multiple steps CMP polishing An improved chemical mechanical polishing apparatus for planarizing semiconductor surface materials. The single rotating polishing platen with an attached pad of conventional CMP processes is replaced with two controlled independently driven, concentric and coplanar, polishing platens. The two co-planar polishing platens allows for separate adjustable options to the CMP polishing process. The options are provided by having pads of different material compositions and hardness. Moreover, an annular space is provided between the platens to introduce the usage of two slurry formulations, one to each pad, on the same CMP tool. The annular space between platens forming a drain path for catching and containing slurry waste. 2003 U. S.Patent
4 Linear polishing for improving substrate uniformity A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts. 2004 U. S.Patent
5 High K artificial lattices for capacitor applications to use in CU or AL BEOL An improved and new process of fabricating high dielectric constant MIM capacitors. These high dielectric constant MIM capacitor met all of the stringent requirements needed for both for both RF and analog circuit applications. For the high dielectric constant MIM capacitor, the metal is com prised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of Super lattices is controlled by the number of layers either 4/4, 2/2, and 1/1 artificial layers. Hence thickness of the film can be easily controlled. Enhancement of dielectric constant is because of interface. Dielectric constants near 900 can be easily achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD. atomic layer CVD techniques is used for this type layer growth process.   2006 U. S.Patent
6 Method of fabricating tensile strained layers and compressive strain layers for a CMOS device. A process for forming both tensile and compressive strained silicon layers to accommodate channel regions of MOSFET or CMOS devices has been developed. After formation of shallow trench isolation structures as well as application of high temperature oxidation and activation procedures, the fabrication sequences used to obtain the strained silicon lay ers is initiated. A semiconductor alloy layer is deposited fol lowed by an oxidation procedure used to segregate a germa nium component from the overlying semiconductor alloy layer into an underlying single crystalline silicon body. The level of germanium segregated into the underlying single crystalline silicon body determines the level of strain, which is in tensile state of a subsequently selectively grown silicon layer. A second embodiment of this invention features the thinning of a portion of the semiconductor alloy layer prior to the oxidation procedure allowing a lower level of germanium to be segregated into a first underlying portion of the under lying single crystalline silicon body, while during the same oxidation procedure a second portion of the underlying single crystalline silicon body receives a higher level of germanium segregation. So the Subsequently deposited silicon-germa nium layer, although the same process and thickness, can be strained in different states (tensile or compressive) and levels, depending different underlying portions’ germanium concen tration.  2008 U. S.Patent
7 An Oximeter device for detecting the arterial blood gas in the transmucosal region of the oral cavity 2020 Indian Filed
8 A device for continuous monitoring of oxygen saturatiin level and pulse rate and the method involved thereof 2020 Indian Filed
// FLASH NEWS //
  • University of Madras attains category - 1 status from UGC |  NIRF Ranking - Ranked 39 in University Category 2024 |  University of Madras has been graded A++ in the NAAC Assessment

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